1. Field of the Invention
The present invention relates to a pulse frequency modulated (PFM) voltage regulator and, more particularly, to a method of reducing a ripple of an output voltage of the PFM voltage regulator in a heavy loading condition.
2. Description of the Related Art
Typically, a voltage regulator is used for supplying an output voltage with a regulated voltage level from a DC voltage source by appropriately controlling a duty cycle of a power switch transistor. Depending on requirements of practical applications, the regulated output voltage may be higher or lower than the original DC voltage source. Of methods for controlling the duty cycle of the power switch transistor in the voltage regulator, the most frequently used are a PFM switching control mode and a pulse width modulated (PWM) switching control mode. The PFM voltage regulator turns on the power switch transistor each time when the output voltage decreases to become equal to a target voltage, thereby regulating the output voltage. On the other hand, the PWM voltage regulator controls the on and off states of the power switch transistor by a rectangular wave having a predetermined duty cycle, thereby achieving the effect of regulating the output voltage.
Neither the PFM voltage regulator nor the PWM voltage regulator can provide the same satisfactory performance when operated both in a light loading condition and in a heavy loading condition. More specifically, the PFM voltage regulator in the heavy loading condition suffers from a great ripple of the output voltage. On the other hand, the PWM voltage regulator has a drawback of becoming a low efficiency regulator in the light loading condition since the power consumption caused by the switching of the power switch transistor becomes relatively large with respect to the output power supplied.
Both of U.S. Pat. No. 5,568,044 and U.S. Pat. No. 6,545,882 have disclosed a PWM voltage regulator characterized in that an original PWM control mode is changed to a PFM control mode in a light loading condition by detecting an inductor current in order to improve the efficiency of the light loading PWM voltage regulator. However, the prior art voltage regulator is required to employ a complicated PWM and PFM dual mode switching circuit.
Alternatively, U.S. Pat. No. 5,801,518 has disclosed a PFM voltage regulator characterized in that an ON-time of the power switch transistor is prolonged and/or an OFF-time of the power switch transistor is shortened in accordance with a degree of decrease for an output voltage. The prior art considers that a longer ON-time may cause more energy to be stored in an inductor and a shorter OFF-time may prevent a capacitor from discharging too much, so the PFM voltage regulator may have an improved output ripple in the heavy loading condition. Contrary to the assumptive consideration, the prior art voltage regulator in practice provides an even larger output ripple. With reference to a paragraph of lines 31 to 35, column 8 in the specification of U.S. Pat. No. 5,801,518, it is assumed that the output voltage of the PFM voltage regulator rises to the maximum possible peak value immediately after the energy stored in the inductor is delivered to the capacitor, i.e. at the instant when the power switch transistor is turned off, and then decreases along with time. As a matter of fact, this assumption cannot be established for a heaving loading PFM voltage regulator, which will be described in more detail later. This is the reason why U.S. Pat. No. 5,801,518 failed to improve the ripple.
FIG. 1(a) is a circuit block diagram showing a conventional PFM voltage regulator 10. Referring to FIG. 1(a), when a power switch transistor Q, such as an NMOS transistor, is at the ON state, a potential at a node A is lower than a potential at an output terminal B, i.e. an output voltage Vout, such that a diode D is unconductive. Therefore, an inductor L stores energy supplied from a DC voltage source Vin, resulting in a linear increase of an inductor current IL. Meanwhile, a capacitor C is discharged to supply a load current Iload, resulting in a decrease of the output voltage Vout at the output terminal B. When the power switch transistor Q is at an OFF state, the energy stored in the inductor L is delivered to the capacitor C through the conductive diode D, thereby raising the output voltage Vout at the output terminal B.
More specifically, a PFM switching controller 11 generates a PFM switching signal 12 for controlling the ON and OFF states of the power switch transistor Q through a driver 13. The PFM switching signal 12 is a pulse signal, each pulse of which may make the power switch transistor Q conductive, for example. In this case, an internal between two consecutive pulses is representative of a period during which the power switch transistor Q is unconductive. The pulse width of the PFM switching signal 12 is in principle a fixed value, which is determined by a constant ON-time controller 14. However, when an over current protection circuit 15 detects that the inductor current IL is higher than a predetermined upper limit of current, the over current protection circuit 15 causes the PFM switching controller 11 to shorten the pulse width of the PFM switching signal 12. On the other hand, the interval between two consecutive pulses of the PFM switching signal 12 is determined by a feedback circuit 16. When the feedback circuit 16 detects that the output voltage Vout at the output terminal B is lower than the target voltage due to the discharge of the capacitor, the feedback circuit 16 causes the PFM switching controller 11 to output a pulse for conducting the power switch transistor Q again. However, the interval between two consecutive pulses are prevented from being shorter than a minimum OFF-time determined by a minimum OFF-time controller 17.
FIG. 1(b) is a waveform timing chart showing an operation of the conventional heavy loading PFM voltage regulator 10 shown in FIG. 1(a). During a period P1, when the output voltage Vout decreases to become lower than the target voltage Vo, i.e. a DC component of the output voltage Vout, the PFM switching signal 12 enters a high level state H with a constant pulse width (or ON-time) TON, con, resulting in the linear increase of the inductor current IL for storing energy in the inductor L. As clearly seen from FIG. 1(b), the output voltage Vout in a heavy loading condition exhibits a considerably large degree of decrease during the constant ON-time TON, con. After the constant ON-time TON, con, the PFM switching signal 12 enters a low level state L such that the energy stored in the inductor L is delivered to the capacitor C, thereby raising the output voltage Vout. However, the output voltage Vout is still lower than the target voltage Vo even after the capacitor C is charged for a minimum OFF-time TOFF, min because in the heavy loading condition a component of the inductor current IL applicable for charging the capacitor C becomes relatively smaller. At this moment, the PFM switching controller 11 causes the PFM switching signal 12 to enter again the high level state H with the constant ON-time TON, con. As clearly seen from FIG. 1(b), during the minimum OFF-time TOFF, min, the energy stored in the inductor L fails to be completely delivered to the capacitor C, which is contrary to the assumption of U.S. Pat. No. 5,801,518, since the inductor current IL does not decrease to zero, resulting in the impossibility of reaching the maximum possible peak value for the output voltage Vout. In this case, during periods P2 and P3 the inductor current IL due to continuous accumulation eventually reaches the upper limit of current Imax, resulting in the shortening of the constant ON-time TON, con of the PFM switching signal 12.
When the power switch transistor Q after switching between on and off many times is turned off again during the period P3, the output voltage Vout finally raises over the target voltage Vo. As a result, the energy continuously stored in the inductor L is completely delivered at a time to the capacitor C, causing a very great output ripple. It takes a significantly long OFF-time for the output voltage Vout to decrease back to the target voltage Vo from the maximum value Vhigh. Thereafter, the PFM switching signal 12 enters the high level state H with the constant ON-time TON, con for turning on the power switch transistor Q to repeat the operations described above. As clearly seen from FIG. 1(b), the output voltage Vout generated from the conventional PFM voltage regulator 10 has a very great ripple 19 in the heavy loading condition.
Since the delivery of the energy between the inductor L and the capacitor C fails to achieve a good efficiency as described above, the conventional PFM voltage regulator 10 inevitably spends an disadvantageously longer time on a transient period from start-up to a stable operational state where the output voltage Vout reaches the target voltage Vo.